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Senin, 08 September 2014
HP USB 3 Button Optical Mouse in Retail Packaging
Minggu, 07 September 2014
Day 3 A Hike to Kleine Scheidegg
The plan for the day was for Phil and I to hike up to Mannlichen, where XiaoQin would join us via cable car. Then hopefully, wed do the mountain view walk together to Kleine Scheidegg and maybe back to Wengen, depending on how much walking we were willing to do. After a short quarter mile walk through Wengen, the trail led steeply up along the hillside. One look up the mountain and it was obvious why---the trail went alongside what was practically a cliff! It didnt take us long before we got to the Felix Mendelssohn Bartholdy memorial. I suspected but didnt know that he was the Mendelssohn, so I took a picture and moved on.
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| From Tour of the Alps 2011 |
Going higher up, the views opened up but because of overcast skies, we could not see far. We had been warned that this hike would be harder than usual because of constructions on the avalanche protection near the top, but were not prepared for signs like this:
![]() |
| From Tour of the Alps 2011 |
In the USA, these signs would be cause for a lawsuit were anyone to be injured by rock fall, and hence the entire trail would be closed, despite the fact that I did not see any possibility of rock fall.
Once we got higher, we saw some wildflowers and the pace slowed a little bit. I wasnt happy about the overcast, though, as it promised that our views of the mountains would be occluded.
![]() |
| From Tour of the Alps 2011 |
Sure enough, the panorama trail granted us only views of the base of the Eiger, the Jungfrau, and the Monch, and the best view of the mountains we got was further down, past the Kleine Scheidegg train station.
![]() |
| From Tour of the Alps 2011 |
We finished the hike one station down, got onto the train and then had a pizza dinner, hoping for some nice weather tomorrow before the serious riding began.
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Kamis, 04 September 2014
PCI Express 3 0 explained
What we do know though is what PCI-Express 3.0 will offer.
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| PCI-Express 3.0 looks the same as PCI-Express 2.0 from the outside |
A Doubling of Bandwidth...
Following the tradition that goes back to AGP (remember that?), the bandwidth is again doubled from 500MB/sec or 4Gb/sec on PCI-Express 2.0 to 1GB/sec or 8Gb/sec on PCI-Express 3.0. Thats per lane, in each direction. This means the total bandwidth for an 16x PCI-Express graphics slots go up from 16GB/s to 32GB/s, so it should cope better with the future demands of high performance graphics cards.
To double the bandwidth the PCI-SIG hasnt just cranked up the transfer frequency by two though, instead its lessened the encoding overheads to make faster transfers more efficient.
| Generation | Bit rate | Interconnect bandwidth | Bandwidth (per lane) | Maximum bandwidth (16 lanes) |
| PCI-Express 1.1 | 2.5GT/sec | 2GB/sec | 250MB/sec | 8GB/sec |
| PCI-Express 2.0 | 5GT/sec | 4GB/sec | 500MB/sec | 16GB/sec |
| PCI-Express 3.0 | 8GT/sec | 8GB/sec | 1GB/sec | 32GB/sec |
... but not a doubling of transfer rate?
Typically PCI-Express (and a whole lot of other signalling buses) use an 8b/10b encoding, which means ten bits are transferred for eight bits (one byte) of actual data. That 20 per cent overhead is considerable, and as weve seen from CPUs, frequencies cannot perpetually increase. This means that this overhead becomes ever more an issue as the bandwith increases.
To work around this problem, PCI-Express 3.0 encodes the data in a much larger 128b/130b chunk, and then a known polynomial is applied to a data stream in a feedback topology, with an inverse polynomial sat at the other end to decode the data. In more human terms, this is basically a hard-coded mathematical function that is designed to evenly spread the 0s and 1s (which are electrical clock blips), so they dont interfere with each other during transport. This technique is called scrambling.
This means the data transfer rate can be lower while still achieving the same real bandwidth. For example, instead of 5GT/sec of PCI-Express 2.0 increasing to 10GT/sec, PCI-E Express 3.0 only needs 8GT/sec. Less transfers mean greater efficiency - so PCI-E Express 3.0 also uses less power - and it doesnt have to use higher grade materials - so the products are cheaper to make. Win-win.
However, PCI-E Express 3.0 provides no more power than its predecesors - but thats actually a good thing. Having >300W drawn from each 16xPCI-E slot would drive up the cost of motherboards, as the copper traces on the motherboard would need to be thicker. Manufacturers might even need to add extra layers to try and route these high power traces and their associated electromagnetic interference away from sensitive data traces.
Finally, PCI-E Express 3.0 has the same physical characteristics as PCI-E Express 2.0, so its backward compatible with previous versions of PCI-Express, regardless of the data encoding change.
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